CLOCK SIGNALS The on-chip phase locked loop (PLL) can be selected to reference the input sample rate from either of the LRCLK pins or 256, 384, 512, or 768 times the sample rate, referenced to the 48 kHz mode from the MCLKI/XI pin. The default at power-up is 256 × fS from the MCLKI/XI pin. In 96 kHz mode, the master clock frequency stays at the same absolute frequency; therefore, the actual multiplication rate is divided by 2. In 192 kHz mode, the actual multiplication rate is divided by 4.
とありますので、MCLK周波数は固定でDAC Control Register0 のSample Rateを192KHz(なので"10"）、 ADC COntrol Register0のOutput Sample Rateも念のために192ｋHz(="10")に設定すれば良いような気がします。
AD1938 Codec "Two of the four serial input ports are connected to the AD1938 ADCs, and all four of the serial output ports are connected to the AD1938 DACs. This provides a total of four channels of analog audio input and eight channels of analog audio output. The AD1938 is hardwired in standalone mode, and its serial ports are configured as slaves. Therefore, the corresponding serial ports on the ADAU1452 must be set as clock masters. By default, all serial ports on the ADAU1452 are set as clock masters when a new project is created in SigmaStudio. The AD1938 is configured to run at a sample rate of 44.1 kHz or 48 kHz. It is not possible to change this setting. Even though the ADAU1452 is very flexible and can run at any sample rate up to 192 kHz, the analog audio inputs and outputs on the EVAL-ADAU1452MINIZ may be distorted or silent if a sample rate other than 44.1 kHz or 48 kHz is used for the ADAU1452 serial ports."